Principal DV Engineer
@ E-SpacePrincipal DV Engineer
This job is still taking applications, but it's been up a while.
About the job
E-Space is innovating space-based communication with advanced LEO satellite systems. The role involves verifying ASICs, leading verification efforts, and supporting space IoT solutions. A passion for space, verification, and leadership is essential.
Requirements
- Expert in Verilog and SystemVerilog
- Experience with UVM environments
- Proficient in C/C++ coding
- Strong scripting in Perl or Python
- Leadership in verification projects
Qualifications
- 10+ years in verification
- Experience in semiconductor industry
- Deep space satellite component knowledge
- Passion for space tech
- Leadership skills
Full job description
Requirements
HDL & Verification Methodology
· Expert-level proficiency in Verilog and SystemVerilog
· Proven experience building UVM verification environments from scratch
· Deep understanding of verification methodologies and best practices
Programming & Scripting
· Proficient in C/C++ coding for verification purposes
· Strong scripting skills in Perl or Python
· Ability to write and maintain bash scripts for verification flows
Verification Planning & Execution
· Experience writing comprehensive test plans
· Experience writing and maintaining test suites
· Ability to debug complex RTL simulations
· Ability to debug gate-level simulations with SDF back-annotation
· Ability to assess whether SDF timing violations are benign or require attention
Leadership
· Proven track record leading code coverage closure
· Experience leading design verification efforts through chip tapeout
What you bring to this role:
10+ years of design verification experience in the semiconductor industry
Additional Requirements
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